R1LV0816ASA-5SI Datasheet, PDF (17/19 Pages) Renesas Technology Corp – 8Mb Advanced LPSRAM (512k word x 16bit / 1M word x 8bit)

R1LV0816ASA –5SI, 7SI
Data Retention Characteristics
Parameter
Symbol Min. Typ. Max. Unit
Test conditions^*3
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
V_CC for data retention
V_DR
1.5
-
3.6
V ^{(2) CS1# ≥ VCC-0.2V,}
CS2 ≥ V_CC-0.2V or
(3) LB# = UB# ≥ V_CC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ V_CC-0.2V
-
1.2^*1
4
Vcc=3.0V, Vin ≥ 0V
μA ~+25°C _{BYTE# ≥ Vcc -0.2V or}
BYTE# ≤ 0.2V
-
3^*2
6
μA ~+40°C _{(1) 0V ≤ CS2 ≤ 0.2V or}
Data retention current
I_CCDR
-
-
(2) CS1# ≥ V_CC-0.2V,
-
15 μA ~+70°C ^{CS2 ≥ V}CC^{-0.2V or}
(3) LB# = UB# ≥ V_CC-0.2V,
-
20
μA ~+85°C
CS1# ≤ 0.2V,
CS2 ≥ V_CC-0.2V
Chip select to data retention time t_CDR
0
-
-
ns
See retention waveform.
Operation recovery time
t_R
5
-
-
ms
Note 1.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+25°C), and not 100% tested.
2.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+40°C), and not 100% tested.
3.CS2 controls address buffer, WE# buffer, CS1# Buffer, OE# buffer, LB#, UB# buffer and Din buffer.
If CS2 controls data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ V_CC-0.2V or 0V ≤ CS2 ≤ 0.2V .
The other inputs levels (address, WE#, OE#, CS1#, LB#, UB#, DQ) can be in the high impedance state.
REJ03C0395-0100 Rev.1.00 2009.12.08
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