HM64YGB36100_15 Datasheet, PDF (17/23 Pages) Renesas Technology Corp – 32M Synchronous Late Write Fast Static RAM (1-Mword × 36-bit)

HM64YGB36100 Series
TAP AC Operating Characteristics
(Ta = 0 to +85°C)
Parameter
Symbol
Min
Max
Unit
Note
Test clock cycle time
tTHTH
67

ns
Test clock high pulse width
tTHTL
30

ns
Test clock low pulse width
tTLTH
30

ns
Test mode select setup
tMVTH
10

ns
Test mode select hold
tTHMX
10

ns
Capture setup
tCS
10

ns
1
Capture hold
tCH
10

ns
1
TDI valid to TCK high
tDVTH
10

ns
TCK high to TDI don’t care
tTHDX
10

ns
TCK low to TDO unknown
tTLQX
0

ns
TCK low to TDO valid
tTLQV

20
ns
Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions
Temperature
Input timing measurement reference level
Input pulse levels
Input rise/fall time
Output timing measurement reference level
Test load termination supply voltage (V_T)
Output load
Boundary Scan AC Test Load
DUT
TDO
0°C ≤ Ta ≤ +85°C
1.1 V
0 to 2.5 V
1.5 ns typical (10% to 90%)
1.25 V
1.25 V
See figure below
V_T
Z₀ = 50 Ω
50 Ω
(V_DD = 2.5 V)
Rev.1.00 Jun 27, 2005 page 15 of 19