R32C120 Datasheet, PDF (16/98 Pages) Renesas Technology Corp – RENESAS MCU

Under development
R32C/120 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
2. Central Processing Unit (CPU)
2.1.8.5 Register Bank Select Flag (B flag)
This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the
register bank 1 is selected.
2.1.8.6 Overflow Flag (O flag)
This flag becomes 1 if an operation results in an overflow; in all other cases, this flag becomes 0.
2.1.8.7 Interrupt Enable Flag (I flag)
This flag enables a maskable interrupt. It indicates 0 when an interrupt is disabled, and 1 when an
interrupt is enabled. Once an interrupt is accepted, the flag is set to 0.
2.1.8.8 Stack Pointer Select Flag (U flag)
This flag indicates 0 when the interrupt stack pointer (ISP) is selected, and 1 when the user stack
pointer (USP) is selected.
It is set to 0 when a hardware interrupt is accepted or the INT instruction whose software interrupt
number is 0 to 127 is executed.
2.1.8.9 Floating-point Underflow Flag (FU flag)
This flag becomes 1 if a floating point operation results in an underflow; in all other cases, this flag
becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.10 Floating-point Overflow Flag (FO flag)
This flag becomes 1 if a floating point operation results in an overflow; in all other cases, this flag
becomes 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).
2.1.8.11 Processor Interrupt Priority Level (IPL)
The 3-bit processor interrupt priority level (IPL) specifies eight processor interrupt priority levels from 0
to 7. If a requested interrupt's priority level is higher than the processor interrupt priority level (IPL), this
interrupt is enabled.
If the processor interrupt priority level (IPL) is set to 111b (level 7), any interrupt is disabled.
2.1.8.12 Fixed-point Designation Bit (DP bit)
This bit designates a fixed point. It also designates which part of the multiplication result should be
taken. It is used for MULX instruction.
2.1.8.13 Floating-point Rounding Mode (RND)
The 2-bit floating point rounding mode designates a rounding mode for the operation result.
2.1.8.14 Reserved
The fields are written with 0. The read value is undefined.
REJ03B0236-0050 Rev.0.50 Jul 31, 2008
Page 16 of 96