R1QBA7236ABG Datasheet, PDF (16/39 Pages) Renesas Technology Corp – 72-Mbit DDRII+ SRAM 2-word Burst

R1QBA72 / R1QEA72 Series
Bus Cycle State Diagram
/LD = H & Count = 2
/LD = H
NOP
Supply
voltage
provided
Power
Up
R-/W = L
/LD = L
&
Count = 2
Write Double
Count
= Count + 2
/LD = L
Load New
Address
Count = 0
R-/W = H
/LD = L
&
Count = 2
Read Double
Count
= Count + 2
/LD = H & Count = 2
Notes:
1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at
the end of this sequence (burst count = 2).
2. State machine control timing sequence is controlled by K.
Rev. 0.11 : 2013.01.15
R10DS0181EJ0011
PAGE:16