R1Q3A3636 Datasheet, PDF (16/26 Pages) Renesas Technology Corp – 36-Mbit QDR™II SRAM 4-word Burst

R1Q3A3636/R1Q3A3618/R1Q3A3609
Timing Waveforms
Read and Write Timing
1
2
3
4
5
6
7
8
9
NOP
READ
WRITE
READ
WRITE
NOP
NOP
NOP
K
tKHKH
/K
tKHKL
tKLKH
tKH/KH
t/KHKH
/R
tIVKH
tKHIX
/W
Address
tIVKH
tKHIX
A0
A1
A2
A3
tAVKH
Data in
tKHAX
D10 D11 D12 D13 D30 D31 D32 D33
tDVKH
tKHDX
tDVKH
tKHDX
Qx3
Data out
CQ
-tCHQX1
Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23
tCHQV
-tCHQX
tCHQV
-tCHQX
tCHQZ
tCQHQV
-tCQHQX
tCHCQV
-tCHCQX
/CQ
C
tKHCH tKHKH
/C
tKHKL
tKLKH
tCHCQV
-tCHCQX
tKH/KH
t/KHKH
tKHCH
Notes: 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following
A0, i.e., A0+1.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded immediately
as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data in.
REJ03C0295-0003 Rev.0.03 Jul. 31, 2007
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