M66239FP Datasheet, PDF (16/24 Pages) Renesas Technology Corp – High Speed Standard Clock Generator With Frequency Synthesizer

M66239FP
Frequency Modulation Resister
Resister
Name
Resister 1
Resister 2
Resister 3
Resister 4
Function
Operation
mode
Modulation
period
Modulation
start position
Center
frequency
Resister 5 Peak
frequency
Resister 6 1st-pole
position
Resister 7 2nd-pole
position
Resister 8 3rd-pole
position
Resister 9 4th-pole
position
Resister 10 1st-pole
frequency
(Mode 4)
Resister 11 3rd-pole
frequency
(Mode 4)
Resister 12 Modulation
resolution
Resister 13 Output phase
control
Address Bit
Setting Range
Default Value
A3 A0 Number
D15
···
D0 D15
···
D0
0 0 0 0 3 bit min 0000000000000001 0000000000000001(1 dec)
max 0000000000000100 * Mode1 when 1 dec
Unit 1LSB
—
0001
0010
0011
16 bit
10 bit
9 bit
min 0000010111011100
max 1111111111111111
min 0000000001100100
max 0000001111111111
min 0000000000000000
max 0000000111111111
* –2.55% when min. value
* +2.55% when max. value
0010000000000000(8192 dec) MCLK cycle
0000000100000000(256 dec) MCLK cycle
0000000100000000(256 dec)
* 0% when 256 dec
* Modulate to + side more than 256 dec
* Modulate to – side less than 256 dec
MCLK frequency
×0.01%
0100
8 bit
min 0000000000011110
max 0000000011111111
* ±0.30% when min. value
* ±2.55% when max. value
0000000011111111(255 dec)
* ±2.55% when 255 dec
MCLK frequency
×0.01%
0101
0110
0111
1000
1001
16 bit
16 bit
16 bit
16 bit
9 bit
min 0000000111110100
max 1001111111111111
min 0000000111110100
max 1001111111111111
min 0000000111110100
max 1001111111111111
min 0000000111110100
max 1001111111111111
min 0000000000000000
max 0000000111111111
* –2.55% when min. value
* +2.55% when max. value
0000011001100110(1638 dec) MCLK cycle
0000110011001100(3276 dec) MCLK cycle
0001001100110010(4914 dec) MCLK cycle
0001100110011000(6552 dec) MCLK cycle
0000000010000000(128 dec) MCLK frequency
* –1.28% when 128 dec
×0.01%
1010
9 bit
min 0000000000000000
max 0000000111111111
* –2.55% when min. value
* +2.55% when max. value
0000000110000000(384 dec)
* +1.28% when 384 dec
MCLK frequency
×0.01%
1 0 1 1 1 bit min 0000000000000000 0000000000000000(0 dec)
—
max 0000000000000001 * 0.01% mode when 0 dec
* ±0.01% mode when min.
* ±0.005% mode when max.
1100
3 bit
min 0000000000000000
max 0000000000000111
* Delay 0 when min.
* Delay 7T/8 when max.
0000000000000000(0 dec)
* Delay 0 when 0 dec
T/8
(Clock cycle)
Notes: 1. Set to the following value for resister 1.
• For operation mode 1: "0000000000000001"
• For operation mode 2: "0000000000000010"
• For operation mode 3: "0000000000000011"
• For operation mode 4: "0000000000000100"
2. Resister 12 must not change.
3. Above table intend to setting available value of resister, practical limits are described in page 20.
4. Resister 13 is for phase control of sync clock output.
5. If the default value of above resister use, write operation to all resister must be done.
6. Resister 6 to 9 refer to following.
• 1st Pole = Tspace1
• 2nd Pole = Tspace1 + Tspace2
• 3rd Pole = Tspace1 + Tspace2 + Tspace3
• 4th Pole = Tspace1 + Tspace2 + Tspace3 + Tspace4
Rev.1.00 Mar 16, 2005 page 16 of 23