M5M5V5A36GP_1 Datasheet, PDF (15/20 Pages) Renesas Technology Corp – 18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM

(4)WRITE TIMING
MITSUBISHI LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
CLK
tckeVKH
CKE#
tEVKH
E#
tKHKH
tKHKL
tKHckeX
tKLKH
tKHEX
tadvVKH
ADV
tWVKH
W#
tKHadvX
tKHWX
tBVKH
BWx#
tKHBX
tAVKH
ADD
DQ
tKHAX
A1
A2
tDVKH
tKHDX
D(A1)
D(A2)
D(A2+1)
A3
A4
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1
D(A4+2)
G#
Write A1 Write A2 Burst Write
A2+1
NOP
Burst Write Write A2 Write A3
A2+3
NOP
Write A4 Burst Write Stall Burst Write Burst Write
A4+1
A4+2
A4+3
DON'T CARE
UNDEFINED
Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note34.ZZ is fixed LOW.
14/19
Preliminary
M5M5V5A36GP REV.0.1