HN58X24128FPIAG Datasheet, PDF (15/22 Pages) Renesas Technology Corp – Two-wire serial interface 128k EEPROM (16-kword ´ 8-bit) 256k EEPROM (32-kword ´ 8-bit)

HN58X24128FPIAG/HN58X24256FPIAG
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for
inputting the more write data. The page write is initiated by a start condition, device address word,
memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition.
The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM
can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last address of the
page, the a0 to a5 address bits will roll over to the first address of the same page and previous write data
will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
128k to
256k
Start
Device
address
1010
1st Memory
address (n)
W
ACK
R/W
2nd Memory
address (n)
Write data (n) Write data (n+m)
ACK
ACK
ACK
ACK
Stop
Notes: 1. Don't care bits for 128k and 256k.
2. Don't care bit for 128k.
13