32170 Datasheet, PDF (142/881 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

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INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
[5] Reading the ICU vector table
Read the ICU vector table for the accepted interrupt request source. The relevant ICU
vector table address can be obtained by zero-extending the content of the Interrupt Vector
Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for
the accepted interrupt request source). The ICU vector table must have set in it the start
address of the interrupt handler for the interrupt request source concerned.)
[6] Enabling multiple interrupts
To enable another higher priority interrupt while processing the accepted interrupt (i.e.,
enabling multiple interrupts), set the PSW register IE bit to "1".
[7] Branching to the internal peripheral I/O interrupt handler
Branch to the start address of the interrupt handler that was read out in [5].
[8] Processing in the internal peripheral I/O interrupt handler
[9] Disabling interrupts
Clear the PSW register IE bit to "0" to disable interrupts.
[10] Restoring the Interrupt Request Mask Register (IMASK)
Restore the Interrupt Request Mask Register that was saved to the stack in [2].
[11] Restoring registers from the stack
Restore the registers that were saved to the stack in [1].
[12] Completion of external interrupt processing
Execute the RTE instruction to complete the external interrupt processing. The program
returns to the state in which it was before the currently processed interrupt request was
accepted.
(3) Identifying the source of the interrupt request generated
If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt
Request Status Register provided for each internal peripheral I/O to identify the source of the
interrupt request generated.
(4) Enabling multiple interrupts
To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable)
bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure
to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack.
Note: • Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then
the ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from
Internal Peripheral I/O."
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32170/32174 Group User's Manual (Rev. 2.1)