R5F213G2CNNP Datasheet, PDF (14/59 Pages) Renesas Technology Corp – RENESAS MCU

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
R8C/3GC Group
2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0301-0010 Rev.0.10
May 24, 2010
Page 14 of 56