R5F21368WJFP Datasheet, PDF (14/71 Pages) Renesas Technology Corp – RENESAS MCU

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
R8C/36W Group, R8C/36X Group, R8C/36Y Group, R8C/36Z Group
1.3 Block Diagram
Figure 1.5 shows a Block Diagram.
1. Overview
8
8
8
8
51
7
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Peripheral functions
Timers
Timer RA0 (8 bits)
Timer RA1 (8 bits)
Timer RB (8 bits)
Timer RC (16 bits)
Timer RD
(16 bits × 2)
Timer RE (8 bits)
Timer RF (16 bits)
Timer RG (16 bits)
DTC
Watchdog timer
(14 bits)
A/D converter
(10 bits × 16 channels)
UART or
clock synchronous serial I/O
(8 bits × 3 channels)
SSU
(8 bits × 1 channel)
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
CAN module ⁽³⁾
(1 channel)
LIN module
(2 channels)
R8C CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM ⁽¹⁾
RAM ⁽²⁾
Multiplier
Port P6
8
Port P8
7
Figure 1.5 Block Diagram
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. Only in the R8C/36W Group and R8C/36X Group.
REJ03B0315-0010 Rev.0.10
May 17, 2010
Page 14 of 68