HD74ALVC165245A Datasheet, PDF (14/18 Pages) Renesas Technology Corp – 16-Bit Dual-supply Bus Transceiver with 3-state Outputs

HD74ALVC165245A
Switching Characteristics (cont)
(Ta = –40 to 85°C)
• V_CCB = 1.2 V, V_CCA = 1.5±0.1 V
Item
Symbol Min Typ Max Unit Test conditions
Propagation delay t_PLH

5.5 
ns C_L = 30 pF
time
t_PHL

5.5 
R_L = 500 Ω
t_PLH

5.5 
t_PHL

5.5 
Output enable time t_ZH
 7.5  ns C_L = 30 pF
t_ZL
 7.5 
R_L = 500 Ω
t_ZH
 9.0 
t_ZL
 9.0 
Output disable time t_HZ
 6.5  ns C_L = 30 pF
t_LZ
 6.5 
R_L = 500 Ω
t_HZ
 5.5 
t_LZ
 5.5 
From(Input) To(Output)
B
A
A
B
OE
A
OE
B
OE
A
OE
B
Operating Characteristics
Item
Power dissipation
capacitance
Symbol V_CCA (V) V_CCB (V) Min Typ Max Unit Test Conditions
C_PD
3.3
2.5
 40  pF f = 10 MHz
C_L = 0
Power-up considerations
Level-translation devices offer an opportunity for successful mixed-voltage signal design.
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies caused by improperly biased device pins.
Take these precautions to guard against such power-up problems.
1. Connect ground before any supply voltage is applied.
2. Next, power up the control side of the device.
(Power up of V_CCB is first. Next power up is V_CCA.)
3. Tie OE to V_CCB with a pullup resistor so that it ramps with V_CCB.
4. Depending on the direction of the data path, DIR can be high or low.
If DIR high is needed (A data to B bus), ramp it with V_CCB. Otherwise, DIR low is needed (B data to A
bus), ramp it with GND.
Rev.2.00, Jan.07.2004, page 14 of 17