HD49335NPHNP_15 Datasheet, PDF (14/32 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335NP/HNP
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
V_OH
Digital output ADC
(D0 to D9) data
Clamp Level
ADC
data
V_OL
ADCLK × 2 clock
ADCLK × 10 clock
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADC_in
(2)
ADCLK
D0 to D9
(1)
(3)
(4)
(5)
Vth
V_DD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No.
(1)
(2), (3)
(4)
(5)
Timing
Signal fetch time
ADCLK tWH min./tWL min.
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Symbol
tADC1
tADC2, 3
tAHLD4
tAOD5
Min
—
Typ × 0.85
—
—
Typ
(6)
1/2fADCLK
(14.5)
(23.5)
Max
—
Typ × 1.15
—
—
Unit
ns
ns
ns
ns
Rev.1.0, Feb.12.2004, page 12 of 29