English
Language : 

H836094 Datasheet, PDF (139/432 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER R8C FAMILY / R8C/1x SERIES
Section 7 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
n←n+1
Increment address
No
No
Verify data + all 1s ?
Yes
Last address of block ?
Yes
EV bit ← 0
Wait 4 µs
EV bit ← 0
Wait 4µs
No
All erase block erased ?
Yes
Yes
n ≤100 ?
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
Rev. 1.00 Aug. 28, 2006 Page 111 of 400
REJ09B0268-0100