R1QHA7236ABG_15 Datasheet, PDF (13/39 Pages) Renesas Technology Corp – 72-Mbit DDRII+ SRAM 2-word Burst

IIP
R1QHA72 / R1QLA72 Series
ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle)
Status
NOP
Read
(B2)
Read Read Read
(B2) (B2) (B2)
NOP
NOP
NOP
Write
(B2)
Write
(B2)
Write
(B2)
Write
(B2)
Read
(B2)
Read
(B2)
K, /K
Command
Ra Rb Rc Rd
We Wf Wg Wh Ri Rj
DQ
Qa Qa Qb Qb Qc Qc Qd Qd
De De Df Df Dg Dg Dh Dh
Qi Qi Qj
DQ ODT
Enabled
Disabled
Enabled
Disabled
ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle)
Status
NOP
Read
(B4)
-
Read
(B4)
-
NOP
NOP
NOP
Write
(B4)
-
Write
(B4)
-
Read
(B4)
-
K, /K
Command
Ra
Rc
We
Wg
Ri
DQ
Qa Qa Qa Qa Qc Qc Qc Qc
De De De De Dg Dg Dg Dg
Qi Qi Qi
DQ ODT
Enabled
Disabled
Enabled
Disabled
ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle)
Status
NOP
Read
(B2)
Read Read Read
(B2) (B2) (B2)
NOP
NOP
Write
(B2)
Write
(B2)
Write
(B2)
Write
(B2)
Read
(B2)
Read
(B2)
Read
(B2)
K, /K
Command
Ra Rb Rc Rd
We Wf Wg Wh Ri Rj Rk
DQ
Qa Qa Qb Qb Qc Qc Qd Qd
De De Df Df Dg Dg Dh Dh
Qi Qi Qj Qj Qk Qk
DQ ODT
Enabled
Disabled
Enabled
Disabled
ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle)
Status
NOP
Read
(B4)
-
Read
(B4)
-
NOP
NOP
Write
(B4)
-
Write
(B4)
-
Read
(B4)
-
Read
(B4)
K, /K
Command
Ra
Rc
We
Wg
Ri
Rk
DQ
Qa Qa Qa Qa Qc Qc Qc Qc
De De De De Dg Dg Dg Dg
Qi Qi Qi Qi Qk Qk
DQ ODT
Enabled
Disabled
Enabled
Disabled
Notes
1. ODT on/off switching timings are edge aligned with CQ or /CQ.
Rev. 0.11 : 2013.01.15
R10DS0184EJ0011
PAGE:13