R1QEA4436RBG_15 Datasheet, PDF (13/31 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture ( 2.5 Cycle Read latency ) with ODT

R1QEA4436RBG, R1QEA4418RBG
Byte Write Truth Table ( x 36 )
Datasheet
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
↑
-
L
L
L
L
-
↑
L
L
L
L
Write D0 to D8
↑
-
L
H
H
H
-
↑
L
H
H
H
Write D9 to D17
↑
-
H
L
H
H
-
↑
H
L
H
H
Write D18 to D26
↑
-
H
H
L
H
-
↑
H
H
L
H
Write D27 to D35
↑
-
H
H
H
L
-
↑
H
H
H
L
Write nothing
↑
-
H
H
H
H
-
↑
H
H
H
H
Notes:
1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 18 )
Operation
K
/K
/BW0
/BW1
Write D0 to D17
↑
-
L
L
-
↑
L
L
Write D0 to D8
↑
-
L
H
-
↑
L
H
Write D9 to D17
↑
-
H
L
-
↑
H
L
Write nothing
↑
-
H
H
-
↑
H
H
Notes:
1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
R10DS0142EJ0200 Rev.2.00
Aug 01, 2014
Page 13 of 30