R1Q3A7236ABG_15 Datasheet, PDF (13/36 Pages) Renesas Technology Corp – 72-Mbit QDR™II SRAM 4-word Burst

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R1Q3A7236ABG / R1Q3A7218ABG Series
Bus Cycle State Diagram
/R = H
/R = H & R_Count = 4
Read Port NOP ^{/R = L}
R_Init = 0
Supply voltage
provided
Load New Always
Read Address
R_Count = 0
R_Init = 1
/R = L
Read Double
R_Count
= R_Count + 2
&
R_Count = 4
R_Count
=2
Increment
Read Address
by Two^*1
Always
R_Init = 0
Power Up
Supply voltage
provided
Write Port NOP
/W = L
R_Init = 0
/W = H
Load New ^Always Write Double
Write Address
W_Count = 0
/W = L
W_Count
= W_Count + 2
&
W_Count = 4
/W = H & W_Count = 4
W_Count
=2
Increment
Write Address
Always
by Two^*1
Notes:
1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The
address order is always fixed as: xxx…xxx+0, xxx…xxx+1, xxx…xxx+2, xxx…xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously. Read and write cannot be
simultaneously initiated. Read takes precedence.
3. State machine control timing sequence is controlled by K.
Rev. 0.11 : 2013.01.15
R10DS0176EJ0011
PAGE:13