PD16640C_15 Datasheet, PDF (13/18 Pages) Renesas Technology Corp – 300/309-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)

µ PD16640C
Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V,
VSS1 = VSS2 = 0 V)
Parameter
Start pulse delay time
Driver output delay time
Driver output delay time
Input capacitance
Symbol
Condition
MIN.
TYP.
MAX.
Unit
tPLH1
CL = 15 pF
7
12
ns
tPHL1
tPLH21
tPLH31
tPHL21
tPHL31
tPLH22
tPLH32
tPHL22
tPHL32
CI1
CI2
VDD2=3.3 V
VO:0.1 V
2 kΩ +75 pF x 2
→3.2 V
VO:3.2 V
→0.1 V
VDD2=5.0 V
VO:0.1 V
2 kΩ +75 pF x 2
→4.9 V
VO:4.9 V
→0.1 V
STHR(STHL), TA=25 °C
V0-V10, TA = 25 °C
7
12
ns
2.6
µs
3.0
10
µs
2.4
µs
3.2
10
µs
2.2
µs
2.9
10
µs
2.6
µs
3.6
10
µs
10
20
pF
60
100
pF
CI3
STHR(STHL), other than V0-V10,
TA=25 °C
10
15
pF
Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = 0 V, tr = tf = 3.0 ns)
Parameter
Symbol
Condition
Clock pulse width
PWCLK
Clock pulse high period
PWCLK (H)
Clock pulse low period
PWCLK (L)
Data setup time
tSETUP1
Data hold time
tHOLD1
Start pulse setup time
tSETUP2
Start pulse hold time
tHOLD2
INV setup time
tSETUP4
INV hold time
tHOLD4
Start pulse low period
tSPL
Start pulse rise time
tSPR1
Osel=H
tSPR2
Osel=L
Final data timing
tSETUP3
CLK-STB time
tINV
STB-CLK time
tLDT
Time between STB and start pulse tCLK-STB
STB-POL time
tSTB-CLK
CLK↑→STB↑
STB↑ →CLK↑
MIN.
TYP.
MAX.
Unit
18
ns
4
ns
4
ns
4
ns
0
ns
4
ns
0
ns
4
ns
0
ns
2
CLK
100
CLK
103
CLK
1
CLK
1
CLK
1
CLK
7
ns
7
ns
Data Sheet S11269EJ1V1DS00
11