HD404318 Datasheet, PDF (13/68 Pages) Hitachi Semiconductor – 4-bit HMCS400-series microcomputer

HD404318 Series
Note:
SEM/SEMD
REM/REMD
TM/TMD
IE
IM
Allowed
Allowed
Allowed
IAOF
IF
ICSF
ICEF
Not executed
Allowed
Allowed
RAME
RSP
Not executed
Allowed
Inhibited
WDON
Allowed
Not executed
Inhibited
ADSF
Allowed
Inhibited
Allowed
Not used
Not executed
Not executed
Inhibited
WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD
instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is
executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers
$040 MR(0)
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
$3C0
$3FF
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
PC₁₃–PC₀ : Program counter
ST: Status flag
CA: Carry flag
Bit 3
$3FC ST
$3FD PC₁₀
$3FE CA
$3FF PC₃
Bit 2
PC₁₃
PC₉
PC₆
PC₂
Bit 1
PC₁₂
PC₈
PC₅
PC₁
Bit 0
PC₁₁
PC₇
PC₄
PC₀
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
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