R5F21114DFP Datasheet, PDF (123/227 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES

R8C/11 Group
13. Serial Interface
UARTi transmit/receive mode register (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0MR
U1MR
Address
00A016
00A816
After reset
0016
0016
Bit
symbol
Bit name
Function
RW
SMD0 _{Serial interface mode}
select bit⁽²⁾
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
RW
SMD1
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
RW
SMD2
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
RW
CKDIR Internal/external clock
select bit⁽³⁾
0 : Internal clock
1 : External clock⁽¹⁾
RW
STPS _{Stop bit length select bit} 0 : 1 stop bit
1 : 2 stop bits
RW
PRY Odd/even parity select bit Effective when PRYE = 1
0 : Odd parity
RW
1 : Even parity
PRYE Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
Reserved bit
(b7)
Set to “0”
RW
NOTES:
1. Must set the P1_6 bit in the PD1 register to “0” (input).
2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: “0002”, “1002”, “1012”, or “1102”.
3. Must set the CKDIR bit to “0” (internal clock) in UART1.
UARTi transmit/receive control register 0 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C0
U1C0
Address
00A416
00AC16
After reset
0816
0816
Bit
symbol
Bit name
Function
RW
b1 b0
CLK0 BRG count source
0 0 : f1SIO is selected
RW
select bit⁽¹⁾
0 1 : f8SIO is selected
CLK1
1 0 : f32SIO is selected
1 1 : Avoid this setting
RW
Reserved bit
(b2)
Set to “0”
RW
TXEPT Transmit register empty ^{0 : Data present in transmit register (during transmission)}
flag
1 : No data present in transmit register
RO
(transmission completed)
Nothing is assigned.
(b4) ^{When write, set to “0”. When read, its content is indeterminate.}
NCH ^{Data output select bit}
0 : TxDi pin is a pin of CMOS output
1 : TxDi pin is a pin of N-channel open-drain output
RW
CKPOL CLK polarity select bit ^{0 : Transmit data is output at falling edge of transfer clock}
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
RW
and receive data is input at falling edge
UFORM Transfer format select bit 0 : LSB first
RW
1 : MSB first
NOTES:
1. If the BRG count source is switched, set the UiBRG register again.
Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers
Rev.1.20 Jan 27, 2006 page 112 of 204
REJ09B0062-0120