R32C-118A Datasheet, PDF (123/132 Pages) Renesas Technology Corp – R32C/100 Series CPU Core

R32C/118A Group
5. Electrical Characteristics
External bus timing (multiplexed bus)
Read cycle
t _cR
t _su(S-ALE)
CS0 to CS3
t _su(A-ALE)
A23 to A8, BC0 to BC3
t _w(ALE)
t _h(ALE-A)
ALE
A15/D15 to A0/D0,
BC0/D0, BC2/D1
t _su(A-ALE)
t _dis(R-A)
Address
t _d(ALE-R)
t _su(D-R)
t _w(R)
Data
RD
t _su(D-R)
D31 to D8
t _h(R-S)
t _h(R-A)
t _h(R-D)
t _dis(R-D)
t _h(R-D)
Write cycle
CS0 to CS3
A23 to A8, BC0 to BC3
ALE
A15/D15 to A0/D0,
BC0/D0, BC2/D1
WR, WR0 to WR3
D31 to D8
t _cW
t _su(S-ALE)
t _h(W-S)
t _su(A-ALE)
t _h(W-A)
t _w(ALE)
t _su(A-ALE)
t _h(ALE-A)
Address
t _d(ALE-W)
t _su(D-W)
Data
t _w(W)
t _h(W-D)
t _su(D-W)
t _h(W-D)
Measurement conditions
Item
Criterion for VIH
input voltage _VIL
Criterion for VOH
output voltage _VOL
V _CC = 4.2 to 5.5 V
2.5 V
0.8 V
2.0 V
0.8 V
V_CC = 3.0 to 3.6 V
1.5 V
0.5 V
2.4 V
0.5 V
Figure 5.9 External Bus Timing for Multiplexed Bus
R01DS0068EJ0120 Rev.1.20
Dec 10, 2014
Page 123 of 127