R2J20654NP Datasheet, PDF (12/16 Pages) Renesas Technology Corp – Integrated Driver - MOS FET (DrMOS)

R2J20654NP
DEM Operation (ZCD_EN# = "L" in Light load condition)
IL _{0 A}
PWM
GH
GL
Figure 1.2 Typical Signals during DEM
Preliminary
The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-
state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 150 ns (typ.). After the tri-state mode has been entered and GH and GL have become
low, a PWM input voltage of 2.6 V or more is required to make the circuit return to normal operation.
150 ns (t_HOLD-OFF)
150 ns (t_HOLD-OFF)
2.0 V
PWM _{1.4 V}
GH
GL
2.0 V
PWM _{1.4 V}
150 ns (t_HOLD-OFF)
150 ns (t_HOLD-OFF)
GH
GL
Figure 2 PWM Shutdown-Hold Time Signal
R07DS0246EJ0100 Rev.1.00
Jan 25, 2011
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