R1QDA4436RBG_15 Datasheet, PDF (12/31 Pages) Renesas Technology Corp – 144-Mbit QDR™II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

R1QDA4436RBG, R1QDA4418RBG
K Truth Table
Datasheet
Operation
K
/R /W
D or Q
Data in
Write Cycle:
Input
Load address, input write
data on two consecutive
↑
H^*7 L^*8 data
D(A+0) D(A+1) D(A+2) D(A+3)
K and /K rising edges
Input
clock
K(t+1) ↑ /K(t+1) ↑ K(t+2) ↑ /K(t+2) ↑
Read Cycle:
Load address, output read
data on two consecutive
↑
K and /K rising edges
Data out
Output
Q(A+0) Q(A+1) Q(A+2) Q(A+3)
L^*8 × data
Input
clock
/K(t+2) ↑ K(t+3) ↑ /K(t+3) ↑ K(t+4) ↑
NOP (No operation)
↑
H H D = x or Q = High-Z
Standby (Clock stopped)
Stopped x x Previous state
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
H: high level, L: low level, ×: don’t care, ↑: rising edge.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at K clock edges.
/R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
Refer to state diagram and timing diagrams for clarification.
When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, or the
case of K = high, /K = low. This condition is not essential, but permits most rapid restart by overcoming
transmission line charging symmetrically.
If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this operation;
however, it is strongly recommended that this signal be brought high, as shown in the truth table.
This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE operations
on consecutive K clock rising edges is not permitted. The device will ignore the second request.
R10DS0136EJ0202 Rev.2.02
Aug 01, 2014
Page 12 of 30