R1Q5A3636B Datasheet, PDF (12/25 Pages) Renesas Technology Corp – 36-Mbit DDRII SRAM 4-word Burst

R1Q5A3636B/R1Q5A3618B
Output waveform
V_DDQ /2
Test points
V_DDQ /2
Output load condition
0.75 V
V_REF
SRAM
Q
250 Ω
ZQ
Z₀ = 50 Ω
V_DDQ /2
50 Ω
AC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
V_{IH (AC)}
V_REF + 0.2


V
1, 2, 3, 4
Input low voltage
V_{IL (AC)}


V_REF − 0.2
V
1, 2, 3, 4
Notes: 1. All voltages referenced to V_SS (GND).
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: V_{IH (AC)} ≤ V_DDQ + 0.5 V for t ≤ t_KHKH/2
Undershoot: V_{IL (AC)} ≥ −0.5 V for t ≤ t_KHKH/2
Power-up: V_IH ≤ V_DDQ + 0.3 V and V_DD ≤ 1.7 V and V_DDQ ≤ 1.4 V for t ≤ 200 ms
During normal operation, V_DDQ must not exceed V_DD. Control input signals may not have pulse widths less
than t_KHKL (min) or operate at cycle rates less than t_KHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, V_{IL (AC)} or V_{IH (AC)}.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, V_{IL (DC)} or V_{IH (DC)}.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008
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