R1Q2A7236ABB_15 Datasheet, PDF (12/36 Pages) Renesas Technology Corp – 72-Mbit QDR™II SRAM 2-word Burst

Common
R1Q2A7236ABB / R1Q2A7218ABB / R1Q2A7209ABB Series
Byte Write Truth Table ( x 36 )
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Ĺ
-
L
L
L
L
Write D0 to D35
-
Ĺ
L
L
L
L
Write D0 to D8
Ĺ
-
L
H
H
H
-
Ĺ
L
H
H
H
Ĺ
-
H
L
H
H
Write D9 to D17
-
Ĺ
H
L
H
H
Ĺ
-
H
H
L
H
Write D18 to D26
-
Ĺ
H
H
L
H
Ĺ
-
H
H
H
L
Write D27 to D35
-
Ĺ
H
H
H
L
Write nothing
Ĺ
-
H
H
H
H
-
Ĺ
H
H
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 18 )
Operation
K
/K
/BW0
/BW1
Ĺ
-
L
L
Write D0 to D17
-
Ĺ
L
L
Ĺ
-
L
H
Write D0 to D8
-
Ĺ
L
H
Ĺ
-
H
L
Write D9 to D17
-
Ĺ
H
L
Ĺ
-
H
H
Write nothing
-
Ĺ
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 9 ) _{Just Reference except R1Q2A**09 series}
Operation
K
/K
/BW
Ĺ
-
L
Write D0 to D8
-
Ĺ
L
Ĺ
-
H
Write nothing
-
Ĺ
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Rev. 0.11 : 2013.01.15
R10DS0164EJ0011
PAGE:12