R1LP0408C-C Datasheet, PDF (12/14 Pages) Renesas Technology Corp – 4M SRAM (512-kword × 8-bit)

R1LP0408C-C Series
Low V_CC Data Retention Characteristics
(Ta = −20 to +70°C)
Parameter
Symbol Min Typ Max Unit Test conditions*³
V_CC for data retention
V_DR
2   V CS# ≥ V_CC − 0.2 V, Vin ≥ 0 V
Data
retention
current
−5SC
to +70°C
to +40°C
to +25°C
I_CCDR
I_CCDR
I_CCDR
 8
 1.0*² 3
 0.8*¹ 3
µA V_CC = 3.0 V, Vin ≥ 0 V
µA CS# ≥ V_CC − 0.2 V
µA
−7LC
to +70°C
to +40°C
to +25°C
I_CCDR
I_CCDR
I_CCDR
  16 µA
 1.0*² 10 µA
 0.8*¹ 10 µA
Chip deselect to data retention time
t_CDR
Operation recovery time
t_R
0
t_RC*⁴ 
 ns See retention waveform
 ns
Notes: 1. Typical values are at V_CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at V_CC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. t_RC = read cycle time.
Low V_CC Data Retention Timing Waveform (CS# Controlled)
t_CDR
Data retention mode
t_R
V_CC
4.5 V
2.2 V
V_DR
CS#
0V
CS# ≥ V_CC – 0.2 V
Rev.2.00, May.26.2004, page 12 of 12