M5M5T5672TG-25 Datasheet, PDF (12/26 Pages) Renesas Technology Corp – 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

(3)READ TIMING
MITSUBISHI LSIs
M5M5T5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
CLK
tckeVKH
CKE#
tEVKH
E#
tadvVKH
ADV
tWVKH
W#
tKHKH
tKHKL
tKHckeX
tKLKH
tKHEX
tKHadvX
tKHWX
BWx#
tAVKH
tKHAX
ADD
A1
A2
A3
DQ
G#
tKHQX1
Q(A1)
Q(A2)
tKHQV tKHQX
tGLQV
Q(A2+1)
Q(A2+2)
tGHQZ
Q(A2+3)
tGLQX1
Q(A2)
tKHQZ
Q(A3)
Q(A3+1)
Read A1 Read A2 Burst Read Stall Burst Read Burst Read Burst Read Deselect Continue Read A3 Burst Read Burst Read Burst Read
A2+1
A2+2
A2+3
A2
Deselect
A3+1
A3+2
A3+3
DON'T CARE
UNDEFINED
Note28.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note29. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note30.ZZ is fixed LOW.
11/25
Preliminary
M5M5T5672TG REV.0.1