RMWV3216A Datasheet, PDF (11/15 Pages) Renesas Technology Corp – 32Mb Advanced LPSRAM (2M word × 16bit)

RMWV3216A Series
Write Cycle (4) (LB#, UB# CLOCK)
A_0~20
CS1#
CS2
t_WC
Valid address
t_AW
t_CW
t_CW
LB#,UB#
t_AS
t_BW
t_WR
WE#
t_WP ^*28
OE#
V_IH
OE# = “H” level
DQ_0~15
t_DW
t_DH
Valid Data
Note
28. t_WP is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
R10DS0259EJ0100 Rev.1.00
2016.01.06
Page 11 of 13