R2J20658BNP Datasheet, PDF (11/16 Pages) Renesas Technology Corp – Integrated Driver - MOS FET (DrMOS)

R2J20658BNP
Preliminary
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as
long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input
is driven to 7.0 V or less.
The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1
F or more must be connected between the CGND plane and the Reg5V pin.
The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is
more than 4.3 V (typ.), the driver state becomes active (figure 1.1). Supervisor circuit has hysteresis and its shutdown
level of Supervisor is 3.8 V (typ.).
Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5
V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V.
The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator
does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and
the 5 V regulator is not disabled.
Voltages from –0.3 V to VCIN+0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a
resistor, etc., to pull the DISBL# line up to VCIN are both possible.
VCIN
L
H
H
H
DISBL#

L
H
Open
Reg5V
0
Active
Active
Active
Driver State
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
Disable (GL, GH = L)
12 V
VCIN > 7.4 V
VCIN
IN
UVL &
5 V Regulator
Reg5V
To Internal
Logic
Supervisor
Figure 1.1 Typical 12 V Input Application
(Activate Built-in 5 V Regulator)
VCIN
5V
IN
UVL &
5 V Regulator
Reg5V
External 5 V
To Internal
Logic
Supervisor
Figure 1.2 External 5 V Application
R07DS0550EJ0101 Rev.1.01
Sep 30, 2011
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