R1Q2A4436RBG_15 Datasheet, PDF (11/30 Pages) Renesas Technology Corp – 144-Mbit QDR™ II SRAM 2-word Burst

R1Q2A4436RBG, R1Q2A4418RBG
Datasheet
K Truth Table
Operation
K
Write Cycle:
Load address, input write
data on two consecutive
↑
K and /K rising edges
/R /W
Data in
Input
x L data
Input
clock
D or Q
D(A+0)
K(t) ↑
Read Cycle:
Load address, output read
data on two consecutive
↑
C and /C rising edges
Data out
Output
L x data
Input
clock
Q(A+0)
/C(t+1) ↑
NOP (No operation)
↑
H H D = x or Q = High-Z
Standby (Clock stopped)
Stopped x x Previous state
D(A+1)
/K(t) ↑
Q(A+1)
C(t+2) ↑
Notes:
1.
2.
3.
4.
5.
6.
H: high level, L: low level, ×: don’t care, ↑: rising edge.
Data inputs are registered at K and /K rising edges. Data outputs are delivered at C clock edges, except if C
and /C are high, then data outputs are delivered at K clock edges.
/R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
Refer to state diagram and timing diagrams for clarification.
When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low
and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but
permits most rapid restart by overcoming transmission line charging symmetrically.
R10DS0140EJ0200 Rev.2.00
Aug 01, 2014
Page 11 of 29