R1LP5256E_17 Datasheet, PDF (11/13 Pages) Renesas Technology Corp – 256Kb Advanced LPSRAM

R1LP5256E Series
Low Vcc Data Retention Characteristics
Parameter
VCC for data retention
Symbol Min. Typ. Max. Unit
Test conditions^*2
VDR
2.0
-
5.5
V
Vin ≥ 0V,
CS# ≥ Vcc-0.2V
-
0.6^*1
2
A ~+25°C
Data retention current
-
-
3
A ~+40°C _{Vcc=3.0V, Vin ≥ 0V,}
ICCDR
CS# ≥ Vcc-0.2V
-
-
8
A ~+70°C
-
-
10 A ~+85°C
Chip deselect time to data retention
tCDR
0
Operation recovery time
tR
5
-
-
-
-
ns
ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, DQ) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
CS# Controlled
Vcc
2.2V
t_CDR
CS#
4.5V 4.5V
t_R
V_DR
2.2V
CS# ≥ Vcc - 0.2V
R10DS0268EJ0100 Rev.1.00
2017.1.27
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