PD16602_15 Datasheet, PDF (11/18 Pages) Renesas Technology Corp – 312-OUTPUT TFT-LCD FULL COLOR DRIVER

µPD16602
(4) Relatonship with HS and PL/NL
HS
PL/NL
CLK
SPR
(SPL)
tHS-SETUP
Hi-Z
tHS-HOLD
Sampling period
012
tHS-SP
Output period
26 27
012
Caution HS and PL/NL edges have no relationship with clock timing.
Timing Item
Symbol
Description
Horizontal synchronization
setup time
tHS-SETUP
Setup time of PL/NL signal with respect to HS.
Secure 50 nsMIN. at least.
Horizontal synchronization
hold time
tHS-HOLD
PL/NL hold time. Secure 250 nsMIN. at least.
The hold capacitance at this time is at common potential VCOM, but the output
buffer does not reach VCOM, and therefore sampling is not possible.
Sampling start time
tHS-SP
Time for the output buffer to reach VCOM (reset level).
Secure 1.0 µsMIN at least. Sampling is possible at this time.
Input the start pulse at this time.
These characteristics are specified by load constants of 50 kΩ + 100 pF.
(5) Internal sampling delay
CLK
SP1
SP2
td1
td2
td1
td2
DR0 to DR3 (input)
DG0 to DG3 (input)
DB0 to DB3 (input)
Timing Duration
Symbol
Description
CLK-sampling pulse delay
td1
Delay time between CLK signal and rising edge of internal sampling pulse
SPn.
Input an analog image signal with a timing difference of td1 in order to secure
a sufficient sampling period.
Sampling pulse-CLK delay
td2
Delay time between CLK signal and falling edge of internal sampling pulse.
td1 is 22 ±5 ns and td2 is 14 ±5 ns (these are not guaranteed values).
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