DN3687GFPV Datasheet, PDF (107/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Clock Pulse Generators
5.2.2 Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X₁ to V_CL or V_SS and leave pin X₂ open, as shown in
figure 5.10.
V_CL or V_SS
X₁
X₂
Open
Figure 5.10 Pin Connection when not Using Subclock
5.3 Prescalers
5.3.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write
prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider
ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode,
the clock input to prescaler S is determined by the division factor designated by MA2 to MA0 in
SYSCR2.
5.3.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (ø_W/4) as its input clock. The
divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode,
or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins
X₁ and X₂.
Rev.5.00 Nov. 02, 2005 Page 73 of 500
REJ09B0027-0500