H8S2649 Datasheet, PDF (104/766 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 4 Exception Handling
4.6 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the statuses of CCR and EXR after execution of trap instruction exception
handling.
Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
I
0
1
2
1
[Legend]
1:
Set to 1
0:
Cleared to 0
: Retains value prior to execution
CCR
UI


I2 to I0


EXR
T

0
Rev. 2.00 Dec. 05, 2005 Page 66 of 724
REJ09B0200-0200