UPD720101GJ-UEN-A Datasheet, PDF (10/38 Pages) Renesas Technology Corp – USB 2.0 HOST CONTROLLER

µPD720101
1. PIN INFORMATION
Pin Name
I/O
Buffer Type
AD (31 : 0)
CBE (3 : 0)0
PAR
FRAME0
IRDY0
TRDY0
STOP0
IDSEL
DEVSEL0
REQ0
GNT0
PERR0
SERR0
INTA0
INTB0
INTC0
PCLK
VBBRST0
CRUN0
PME0
VCCRST0
SMI0
XT1/SCLK
XT2
DP (5 : 1)
DM (5 : 1)
RSDP (5 : 1)
RSDM (5 : 1)
OCI (5 : 1)
PPON (5 : 1)
LEGC
SRCLK
SRDTA
SRMOD
RREF
NTEST1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
I
I/O
O
O
O
O
I
I
I/O
O
I
O
I
O
I/O
I/O
O
O
I (I/O)
O (I/O)
I (I/O)
O
I/O
I
A
I
5 V PCI I/O
5 V PCI I/O
5 V PCI I/O
5 V PCI I/O
5 V PCI I/O
5 V PCI I/O
5 V PCI I/O
5 V PCI input
5 V PCI I/O
5 V PCI output
5 V PCI input
5 V PCI I/O
5 V PCI N-ch open drain
5 V PCI N-ch open drain
5 V PCI N-ch open drain
5 V PCI N-ch open drain
5 V PCI input
5 V tolerant input
5 V PCI I/O
5 V PCI N-ch open drain
5 V tolerant input
5 V tolerant N-ch open drain
Input
Output
USB high speed D+ I/O
USB high speed D− I/O
USB full speed D+ Output
USB full speed D− Output
Input
Output
Input
Output
I/O
Input with 50 kΩ pull down R
Analog
Input with 12 kΩ pull down R
Active
Level
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
Function
(1/2)
PCI “AD [31 : 0]” signal
PCI “C/BE [3 : 0]” signal
PCI “PAR” signal
PCI “FRAME#” signal
PCI “IRDY#” signal
PCI “TRDY#” signal
PCI “STOP#” signal
PCI “IDSEL” signal
PCI “DEVSEL#” signal
PCI “REQ#” signal
PCI “GNT#” signal
PCI “PERR#” signal
PCI “SERR#” signal
PCI “INTA#” signal
PCI “INTB#” signal
PCI “INTC#” signal
PCI “CLK” signal
Hardware reset for chip
PCI “CLKRUN#” signal
PCI “PME#” signal
Reset for power management
System management interrupt output
System clock input or oscillator in
oscillator out
USB high speed D+ signal
USB high speed D− signal
USB full speed D+ signal
USB full speed D− signal
USB root hub port’s overcurrent status input
USB root hub port’s power supply control output
Legacy support switch
Serial ROM clock out
Serial ROM data
Serial ROM input enable
Reference resistor
Test pin
8
Data Sheet S16265EJ5V0DS