RMQSGA3636DGBA_15 Datasheet, PDF (10/30 Pages) Renesas Technology Corp – 36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency)

RMQSGA3636DGBA, RMQSGA3618DGBA
Preliminary Datasheet
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 15% is between 175 Ω and 350 Ω. The total external capacitance of ZQ ball must be
less than 7.5 pF.
QVLD (Valid data indicator)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid
indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for
capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data.
QVLD is edge aligned with CQ and /CQ.
R10DS0238EJ0002 Rev.0.02
Dec. 01, 2014
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