M64898GP Datasheet, PDF (10/14 Pages) Mitsubishi Electric Semiconductor – PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

M64898GP
Test Mode Data Set Up Method
The data for the test mode uses 20 to 27 bits. Data is latched when the 27th clock signal falls.
1. When transferring 3-wire 27 bit data
ENA
CLK
1
Band Switch
Data
M Counter Divider
Ratio Setting
19 20
S Counter Divider
Ratio Setting
X X T2 T1 T0 RSa RSb OS
Test Data Setting
Read Into Latch
2. Test Mode Bit Set Up
X
: Random, 0 or 1 normal “0”
T0, T1 & T2 : Set up test modes
RSa, Rsa : Set the frequency divider of the reference frequency
OS
: Set up the tuning amplifier
Setting Up for The Test mode
T2
T1
T0
Charge Pump
0
0
X Normal operation
0
1
X High impedance
1
1
0 Sink
1
1
1 Source
1
0
0 High impedance
1
0
1 High impedance
Pin 12 Condition
LD
LD
LD
LD
f_REF
f1/N
Mode
Normal operation
Test mode
Test mode
Test mode
Test mode
Test mode
RSa, RSb: Set Up for The Reference Frequency Divider Ratio
RSa
RSb
1
1
0
1
X
0
Divider Ratio
1/512
1/1024
1/640
OS: Set Up The Tuning Amplifier
OS
0
1
Tuning Voltage Output
ON
OFF
Mode
Normal
Test
Power On Reset Operation
(Initial state the power is turned ON)
BS4 to BS1
Charge pump
Tuning amplifier
Charge pump current
Frequency divider ratio
Lock detect
: OFF
: High impedance
: OFF
: 270 µA
: 1/1024
:H
Charge pump current is replaced by 70 µA when locks it by automatic change facility.
Rev.2.00 Jun 14, 2006 page 10 of 13