HM628512C Datasheet, PDF (10/19 Pages) Hitachi Semiconductor – 4 M SRAM (512-kword x 8-bit)

HM628512C Series
Write Cycle
HM628512C
-5
-7
Parameter
Symbol Min Max Min Max Unit Notes
Write cycle time
t _WC
55
—
70
—
ns
Chip selection to end of write
t _CW
50
—
60
—
ns
4
Address setup time
t _AS
0
—
0
—
ns
5
Address valid to end of write
t _AW
50
—
60
—
ns
Write pulse width
t _WP
40
—
50
—
ns
3, 12
Write recovery time
t _WR
0
—
0
—
ns
6
WE to output in high-Z
t _WHZ
0
20
0
25
ns
1, 2, 7
Data to write time overlap
t _DW
25
—
30
—
ns
Data hold from write time
t _DH
0
—
0
—
ns
Output active from output in high-Z
t _OW
5
—
5
—
ns
2
Output disable to output in high-Z
t _OHZ
0
20
0
25
ns
1, 2, 7
Notes: 1. t_HZ, t_OHZ and t_WHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t_WP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. t_WP is measured from the beginning of write to the end of write.
4. t_CW is measured from CS going low to the end of write.
5. t_AS is measured from the address valid to the beginning of write.
6. t_WR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE low fixed, t_WP must satisfy the following equation to avoid a problem of
data bus contention. t_WP ≥ t_DW min + t_WHZ max
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