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HD74ALVC165245A_05 Datasheet, PDF (10/14 Pages) Renesas Technology Corp – 16-Bit Dual-supply Bus Transceiver with 3-state Outputs
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HD74ALVC165245A
Switching Characteristics (cont.)
Item
Symbol Min
Typ
Propagation delay time tPLH

4.5
tPHL

4.5
tPLH

5.0
tPHL

5.0
Output enable time
tZH

6.5
tZL

6.5
tZH

9.0
tZL

9.0
Output disable time
tHZ

5.5
tLZ

5.5
tHZ

5.5
tLZ

5.5
(VCCB = 1.2 V, VCCA = 1.8±0.15 V, Ta = –40 to 85°C)
Max Unit Test conditions From(Input) To(Output)

ns CL = 30 pF
B
A

RL = 500 Ω

A
B


ns CL = 30 pF
OE
A

RL = 500 Ω

OE
B


ns CL = 30 pF
OE
A

RL = 500 Ω

OE
B

(VCCB = 1.2 V, VCCA = 1.5±0.1 V, Ta = –40 to 85°C)
Item
Symbol Min
Typ
Max Unit Test conditions From(Input) To(Output)
Propagation delay time tPLH

5.5

ns CL = 30 pF
B
A
tPHL

5.5

RL = 500 Ω
tPLH

5.5

A
B
tPHL

5.5

Output enable time
tZH

7.5

ns CL = 30 pF
OE
A
tZL

7.5

RL = 500 Ω
tZH

9.0

OE
B
tZL

9.0

Output disable time
tHZ

6.5

ns CL = 30 pF
OE
A
tLZ

6.5

RL = 500 Ω
tHZ

5.5

OE
B
tLZ

5.5

Operating Characteristics
Item
Symbol VCCA (V)
VCCB (V)
Min
Typ
Max Unit
Test Conditions
Power dissipation CPD
3.3
2.5

40

pF f = 10 MHz
capacitance
CL = 0
Power-up considerations
Level-translation devices offer an opportunity for successful mixed-voltage signal design.
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations,
or other anomalies caused by improperly biased device pins.
Take these precautions to guard against such power-up problems.
1. Connect ground before any supply voltage is applied.
2. Next, power up the control side of the device.
(Power up of VCCB is first. Next power up is VCCA.)
3. Tie OE to VCCB with a pullup resistor so that it ramps with VCCB.
4. Depending on the direction of the data path, DIR can be high or low.
If DIR high is needed (A data to B bus), ramp it with VCCB. Otherwise, DIR low is needed (B data to A bus), ramp
it with GND.
Rev.2.01 Apr. 11, 2005 page 10 of 13
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