HD49338F Datasheet, PDF (10/23 Pages) Renesas Technology Corp – CDS/PGA & 12-bit A/D Converter

HD49338F/HF
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
1
2
• When CDSIN input mode is used
~
11
12
13
CDSIN
N
N+1
N+2
N+11
N+12
N+13
SPBLK
SPSIG
ADCLK
D0 to D11
N−12
N−11
N−10
N−1
N
• When ADCIN input mode is used
N
ADCIN
N+1
N+2
N+10
N+11
N+12
N+13
ADCLK
D0 to D11
N−11
N−10
N−1
N
N+1
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
The ADC output (D0 to D11) is output at the rising edge of the ADCLK in both modes.
Pipe-line delay is twelve clock cycles when CDSIN is used and eleven when ADCIN is used.
In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Apr 20, 2004, page 10 of 22