3806_03 Datasheet, PDF (10/223 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M38063M6-XXXFP .......................................................................... 1-2
Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP ............................. 1-3
Fig. 3 Functional block diagram .................................................................................................. 1-4
Fig. 4 Part numbering ................................................................................................................... 1-7
Fig. 5 Memory expansion plan .................................................................................................... 1-8
Fig. 6 Memory expansion plan (Extended operating temperature version) ........................ 1-10
Fig. 7 Memory expansion plan (High-speed version) ............................................................ 1-11
Fig. 8 740 Family CPU register structure ................................................................................ 1-12
Fig. 9 Register push and pop at interrupt generation and subroutine call ........................ 1-13
Fig. 10 Structure of CPU mode register .................................................................................. 1-15
Fig. 11 Memory map diagram .................................................................................................... 1-16
Fig. 12 Memory map of special function register (SFR) ....................................................... 1-17
Fig. 13 Port block diagram (single-chip mode) (1)................................................................. 1-19
Fig. 14 Port block diagram (single-chip mode) (2)................................................................. 1-20
Fig. 15 Interrupt control .............................................................................................................. 1-22
Fig. 16 Structure of interrupt-related registers ........................................................................ 1-22
Fig. 17 Structure of timer XY register ...................................................................................... 1-23
Fig. 18 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-24
Fig. 19 Block diagram of clock synchronous serial I/O1 ....................................................... 1-25
Fig. 20 Operation of clock synchronous serial I/O1 function ............................................... 1-25
Fig. 21 Block diagram of UART serial I/O ............................................................................... 1-26
Fig. 22 Operation of UART serial I/O function ....................................................................... 1-27
Fig. 23 Structure of serial I/O control registers ...................................................................... 1-28
Fig. 24 Structure of serial I/O2 control register ...................................................................... 1-29
Fig. 25 Block diagram of serial I/O2 function ......................................................................... 1-29
Fig. 26 Timing of serial I/O2 function....................................................................................... 1-30
Fig. 27 Structure of AD/DA control register ............................................................................ 1-31
Fig. 28 Block diagram of A-D converter .................................................................................. 1-31
Fig. 29 Block diagram of D-A converter .................................................................................. 1-32
Fig. 30 Equivalent connection circuit of D-A converter ......................................................... 1-32
Fig. 31 Example of reset circuit ................................................................................................ 1-33
Fig. 32 Internal status of microcomputer after reset .............................................................. 1-33
Fig. 33 Timing of reset ............................................................................................................... 1-34
Fig. 34 Ceramic resonator circuit .............................................................................................. 1-35
Fig. 35 External clock input circuit ........................................................................................... 1-35
Fig. 36 Block diagram of clock generating circuit .................................................................................. 1-35
Fig. 37 Memory maps in various processor modes ............................................................... 1-36
Fig. 38 Structure of CPU mode register .................................................................................. 1-36
Fig. 39 ONW function timing ...................................................................................................... 1-37
Fig. 40 Programming and testing of One Time PROM version ........................................... 1-39
Fig. 41 Timing chart after an interrupt occurs ........................................................................ 1-41
Fig. 42 Time up to execution of the interrupt processing routine ....................................... 1-41
Fig. 43 A-D conversion equivalent circuit ................................................................................ 1-43
Fig. 44 A-D conversion timing chart ......................................................................................... 1-43
3806 GROUP USER’S MANUAL
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