UPD720201K8-701-BAC-A Datasheet, PDF (1/43 Pages) Renesas Technology Corp – ASSP (USB3.0 HOST CONTROLLER)

Data Sheet
μPD720201/μPD720202
ASSP (USB3.0 HOST CONTROLLER)
R19DS0047EJ0500
Rev.5.00
Jan. 17, 2013
1. OVERVIEW
The μPD720201 and μPD720202 are Renesas’ third generation Universal Serial Bus 3.0 host controllers,
which comply with Universal Serial Bus 3.0 Specification, and Intel’s eXtensible Host Controller Interface
(xHCI). These devices reduce power consumption and offer a smaller package foot-print making them ideal
for designers who wish to add the USB3.0 interface to mobile computing devices such as laptops and
notebook computers.
The μPD720201 supports up to four USB3.0 SuperSpeed ports and the μPD720202 supports up to two
USB3.0 SuperSpeed ports. The μPD720201 and μPD720202 use a PCI Express® Gen 2 system interface
bus allowing system designers to easily add up to four (μPD720201) or two (μPD720202) USB3.0
SuperSpeed ports to systems containing the PCI Express bus interface. When connected to USB 3.0-
compliant peripherals, the μPD720201 and μPD720202 can transfer information at clock speeds of up to 5
Gbps. The μPD720201 and μPD720202 and USB3.0 standard are fully compliant and backward compatible
with the previous USB2.0 standard. The new USB3.0 standard supports data transfer speeds of up to ten
times faster than those of the previous-generation USB2.0 standard, enabling quick and efficient transfers of
large amounts of information.
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Features
z Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB
Implementers Forum, Inc
- Supports the following speed data rate as follows: Low-Speed (1.5 Mbps) / Full-Speed (12
Mbps) / Hi-Speed (480 Mbps) / SuperSpeed (5 Gbps)
- μPD720201 supports up to 4 downstream ports for all speeds
- μPD720202 supports up to 2 downstream ports for all speeds
- Supports all USB compliant data transfer types as follows; Control / Bulk / Interrupt /
Isochronous transfer
z Compliant with Intel’s eXtensible Host Controller Interface (xHCI) Specification Revision 1.0
- Supports USB debugging capability on all SuperSpeed ports.
z Supports USB legacy function
z Compliant with PCI Express Base Specification Revision 2.0
z Supports Latency Tolerance Reporting ECN of PCI Express Specification
z Supports ExpressCard^TM Standard Release1.0
z Supports PCI Express Card Electromechanical Specification Revision 2.0
z Supports PCI Bus Power Management Interface Specification Revision 1.2
z Supports USB Battery Charging Specification Revision 1.2 and other portable devices
- DCP mode of BC 1.2
- CDP mode of BC 1.2
- China Mobile Phone Chargers
- EU Mobile Phone Chargers
- Apple iOS products
z Operational registers are direct-mapped to PCI memory space
z Supports Serial Peripheral Interface (SPI) type ROM for Firmware
z Supports Firmware Download Interface from system BIOS or system software
z System clock: 24 MHz crystal
R19DS0047EJ0500 Rev. 5.00
Jan. 17, 2013
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