SN74AUP2G126 Datasheet, PDF (1/16 Pages) Texas Instruments – LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AUP2G126
LOW-POWER DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES687B – JANUARY 2007 – REVISED JANUARY 2008
FEATURES
1
•2 Available in the Texas Instruments NanoFree™
Package
• Low Static-Power Consumption
(I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption
(C_pd = 4 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot
<10% of V_CC
• Input-Disable Feature Allows Floating Input
Conditions
• I_off Supports Partial-Power-Down Mode
Operation
• Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at Input
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 4.6 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
P^{3421 REVIE8576W}
V_CC
2OE
1Y
2A
RSE PACKAGE
(TOP VIEW)
2OE 1 8 _{7 1OE}
1Y
2A
3_P^{2 RE}₄^VIE56^W
1A
2Y
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 ^VCC
YFP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 V_CC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figure 1 and Figure 2).
Static-Power Consumption
(mA)
100%
80%
60%
40%
3.3-V
Logic^†
Dynamic-Power Consumption
(pF)
100%
80%
60%
40%
3.3-V
L_LV_oC_gic†
20%
0%
20%
AUP
0%
AUP
† _{Single, dual, and triple gates}
Switching Characteristics
at 25 MHz^†
3.5
3
2.5
2
Input
Output
1.5
1
0.5
0
-0.5
0 5 10 15 20 25 30 35 40 45
Time - ns
† _{AUP1G08 data at CL = 15 pF}
Figure 1. AUP – The Lowest Power Family
Figure 2. Excellent Signal Integrity
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated