RD74LVC74B Datasheet, PDF (1/9 Pages) Renesas Technology Corp – Dual D-type Flip Flops with Preset and Clear

RD74LVC74B
Dual D-type Flip Flops with Preset and Clear
REJ03D0324–0100Z
Rev.1.00
Jun. 22, 2004
Description
The RD74LVC74B has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The
logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage
and high-speed operation is suitable at the battery drive product (note type personal computer) and low power
consumption extends the life of a battery for long time operation.
Features
• V_CC = 1.65 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±4 mA (@V_CC = 1.65 V)
±8 mA (@V_CC = 2.3 V)
±12 mA (@V_CC = 2.7 V)
±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
RD74LVC74BFPEL
RD74LVC74BTELL
SOP–14 pin (JEITA)
TSSOP–14 pin
FP–14DAV
TTP–14DV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs / reel)
ELL (2,000 pcs / reel)
Function Table
L
H
L
H
H
H
H
H
H:
L:
X:
↓:
↑:
Q₀:
Note:
Inputs
Outputs
PR
CLR
CK
D
Q
Q
H
X
X
H
L
L
X
X
L
H
L
X
X
H^*1
H^*1
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q₀
Q₀
H
H
X
Q₀
Q₀
H
↓
X
Q₀
Q₀
High level
Low level
Immaterial
High to Low transition
Low to high transition
Level to Q before the indicated steady input conditions were established.
1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and
clear go high simultaneously.
Rev.1.00 Jun. 22, 2004 page 1 of 8