RD74LVC573B Datasheet, PDF (1/10 Pages) Renesas Technology Corp – Octal D-type Transparent Latches with 3-state Outputs

RD74LVC573B
Octal D-type Transparent Latches with 3-state Outputs
REJ03D0209–0100Z
Rev.1.00
Apr.15.2004
Description
The RD74LVC573B has eight D type latches with three state outputs in a 20-pin package. When the latch enable input
is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at
the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal
computer) and low power consumption extends the life of a battery for long time operation.
Features
• V_CC = 1.65 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V or output off state)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±4 mA (@V_CC = 1.65 V)
±8 mA (@V_CC = 2.3 V)
±12 mA (@V_CC = 2.7 V)
±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
RD74LVC573BFPEL
SOP-20 pin (JEITA) FP-20DAV
FP
RD74LVC573BTELL
TSSOP-20 pin
TTP-20DAV
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs / Reel)
ELL (2,000 pcs / Reel)
Function Table
Inputs
OC
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
H : High level
L : Low level
X : Immaterial
Z : High impedance
Q₀ : Level of Q before the indicated steady input conditions were established.
Output Q
H
L
Q₀
Z
Rev.1.00, Apr.15.2004, page 1 of 9