RD74LVC373B Datasheet, PDF (1/10 Pages) Renesas Technology Corp – Octal D-type Transparent Latches with 3-state Outputs

RD74LVC373B
Octal D-type Transparent Latches with 3-state Outputs
Description
REJ03D0381–0100
Rev.1.00
Nov. 26, 2004
The RD74LVC373B has eight D type latches with three state outputs in a 20 pin package. When the latch enable input
is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at
the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal
computer) and low power consumption extends the life of battery for long time operation.
Features
• V_CC = 1.65 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V or output off state)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±4 mA (@V_CC = 1.65 V)
±8 mA (@V_CC = 2.3 V)
±12 mA (@V_CC = 2.7 V)
±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
RD74LVC373BFPEL
RD74LVC373BTELL
SOP–20 pin (JEITA)
TSSOP–20 pin
FP–20DAV
TTP–20DAV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
G
LE
D
H
X
X
L
H
L
L
H
H
L
L
X
H: High level
L: Low level
X: Immaterial
Z: High impedance
Q₀: Level of Q before the indicated steady input conditions were established.
Output Q
Z
L
H
Q₀
Rev.1.00 Nov. 26, 2004 page 1 of 9