RD74LVC273B Datasheet, PDF (1/9 Pages) Renesas Technology Corp – Octal D-type Flip-Flops with Clear

RD74LVC273B
Octal D-type Flip-Flops with Clear
Description
REJ03D0323–0100Z
Rev.1.00
Jun. 16, 2004
The RD74LVC273B has eight edge trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having
the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The
clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-
powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
• V_CC = 1.65 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High Output current ±4 mA (@V_CC = 1.65 V)
±8 mA (@V_CC = 2.3 V)
±12 mA (@V_CC = 2.7 V)
±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
RD74LVC273BFPEL
RD74LVC273BTELL
SOP–20 pin(JEITA)
TSSOP–20 pin
FP–20DAV
TTP–20DAV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs / reel)
ELL (2,000 pcs / reel)
Function Table
Inputs
CLR
CLK
D
L
X
X
L
H
↑
H
H
H
↑
L
L
H
↓
X
Q₀
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Q₀: Output level before the indicated steady state input conditions were established.
Output Q
Rev.1.00 Jun. 16, 2004 page 1 of 8