RD74LVC126B Datasheet, PDF (1/9 Pages) Renesas Technology Corp – Quad. Bus Buffer Gates with 3-state Outputs

RD74LVC126B
Quad. Bus Buffer Gates with 3-state Outputs
Description
REJ03D0499–0200
Rev.2.00
Dec. 10, 2004
The RD74LVC126B has four bus buffer gates in a 14 pin package. The device requires the three state control input OE
to be taken low to put the output into the high impedance condition. Low voltage and high-speed operation is suitable
at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for
long time operation.
Features
• V_CC = 1.65 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V or output off state)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±4 mA (@V_CC = 1.65 V)
±8 mA (@V_CC = 2.3 V)
±12 mA (@V_CC = 2.7 V)
±24 mA (@V_CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
RD74LVC126BFPEL
RD74LVC126BTELL
SOP–14 pin (JEITA)
TSSOP–14 pin
FP–14DAV
TTP–14DV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
OE
A
L
X
H
L
H
H
H: High level
L: Low level
X: Immaterial
Z: High impedance
Outputs Y
Z
L
H
Rev.2.00 Dec. 10, 2004 page 1 of 8