R8A66174SP Datasheet, PDF (1/12 Pages) Renesas Technology Corp – PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO

R8A66174SP
PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO
REJ03F0278-0101
Rev. 1.01
Oct.06.2008
DESCRIPTION
The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands or up to 63-
bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by
executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request
signal. R8A66174 has 2-bit output pins (/OE, LATCH) which can set/reset outside devices by the command,
R8A66174 can be connected to peripheral circuits that have a serial latch structure. R8A66174 is the
succession product of M66300.
FEATURES
● General-purpose 8-bit CPU bus compatible
● Built-in 63-byte FIFO
● High-speed output (10Mbps)
● It’s able to connect to LED array driver such as R8A66160 or R8A66161 directly
● Low-noise, high-output circuit
IOL=16mA, IOH=-16mA (IOL=4mA, IOH=-4mA for /INT)
● Schmitt input (/RESET)
● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V)
● Wide operating temperature range (Ta=-40~85^oC)
APPLICATION
General digital equipment for industrial and home use, panel display controllers, and eraser unit controller for
copying machine.
PIN CONFIGURATION (TOP VIEW)
WRITE INPUT _WR
1
D0
2
D1
3
D2
4
D3
5
DATA BUS
D4
6
D5
7
D6
8
D7
9
GND 10
20
Vcc
19
C/D
COMMAND/DATA INPUT
18
CS
CHIP SELECT INPUT
17
RESET RESET INPUT
16
INT
INTERRUPT REQUEST OUTPUT
15
OE
OUTPUT ENABLE OUTPUT
14
LATCH LATCH OUTPUT
13
SDATA SHIFT DATA OUTPUT
12
SCLK _{SHIFT CLOCK OUTPUT}
11
Φ
CLOCK INPUT
REJ03F0278-0101 Rev.1.01 Oct.06.2008
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