R1QHA4436RBG_15 Datasheet, PDF (1/30 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

Datasheet
R1QHA4436RBG,R1QHA4418RBG
144-Mbit DDR™II+ SRAM 2-word Burst
Architecture (2.0 Cycle Read latency)
R10DS0145EJ0200
Rev.2.00
Aug 01, 2014
Description
The R1QHA4436RBG is a 4,194,304-word by 36-bit and the R1QHA4418RBG is a 8,388,608-word by 18-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
Features
„ Power Supply
z 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
„ Clock
z
z
z
z
Fast clock cycle time for high bandwidth
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
Clock-stop capability with μs restart
„ I/O
z
z
z
z
z
z
Common data input/output bus
Pipelined double data rate operation
HSTL I/O
User programmable output impedance
PLL circuitry for wide output data valid window and future frequency scaling
Data valid pin (QVLD) to indicate valid data on the output
„ Function
z Two-tick burst for low DDR transaction size
z Internally self-timed write control
z Simple control logic for easy depth expansion
z JTAG 1149.1 compatible test access port
„ Package
z 165 FBGA package (15 x 17 x 1.4 mm)
R10DS0145EJ0200 Rev.2.00
Aug 01, 2014
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